The present invention relates to memories which combine FLASH (sector-erasable) and EEPROM (byte-erasable) memory on a single chip.
Background: Floating-Gate Memories
The development of nonvolatile memories based on the principle of trapping an electrical charge in an isolated (floating) gate of a field effect transistor (cell) in order to modify its turn-on threshold, has had and continues to have an extremely important role in the achievement of ever increasing levels of compactness and of speed of integrated systems.
Programming and Erasure Mechanisms
The development of such memories is strictly tied to a parallel development of suitable fabrication technologies and to the physical mechanisms that can be practically exploited for injecting electrical charges in a floating gate through an isolating dielectric, which often constitutes also the gate dielectric of the (transistor) cell. The physical mechanisms that are normally exploited are the following:
the so-called Fowler-Nordheim tunnelling mechanism that is operative with relatively thick oxide layers and requires a strong electric field; PA1 the direct tunneling mechanism that is operative with relatively thin oxide layers and with a relatively strong electric field; PA1 a "modified" Fowler-Nordheim tunnelling mechanism that is operative with a thin dielectric layer and with an electric field of medium intensity; PA1 the charge-trap assisted injection mechanism wherein charge trapping sites are rearranged at the interface between the conductor and the dielectric and which is effective with thin dielectrics and with a relatively low electric field intensity; PA1 the channel hot carriers injection mechanism that is operative throughout an ample range of dielectric thicknesses and of electric field intensities. PA1 only a small portion of the data stored in a permanent (nonvolatile) manner will be frequently updated; and PA1 a vast mass of data is destined to remain unvaried in time or to be modified only after relatively long intervals of time or only in consequence of exceptional events. Situations of this type are common in the field of automatic control, regulation, self-diagnostic systems and the like. Such systems are increasingly being employed in the car industry and in similar industries, wherein periodically it is necessary to modify/update certain data relative to tests, maintenance, modification of the values of certain parameters of operation and so forth.
Of course, the tunnelling mechanisms may theoretically be exploited also for extracting (discharging) electric charges from the floating gate, that is for electrically "erasing" the cell, even though the voltages that are required must be compatible with the physical-electrical structure of the cell.
The choice of the charge and discharge mechanisms will affect not only the structure of the memory cell itself, but also the overhead (ancillary) circuitry, with a particular regard to writing, reading and eventually also erasing circuits of the memory. This may be illustrated by posing case-by-case precise requisites of voltage and current levels necessary for programming and eventually erasing data stored in the memory, beside those that are required during a reading phase.
EEPROM Memories
The requirement of altering the content of the memory by single bytes (herein intended to constitute a unit of information composed by a certain number of bits, for example 8, 16, 32, etc.) without having to reprogram the entire memory as in the case of the so-called EPROM memories, and therefore the requirement of being able to erase certain selected cells while leaving unchanged the information content of other cells, had led to develop so-called EEPROM or E.sup.2 PROM cells. (Both "EEPROM" and "E.sup.2 PROM" are acronyms of Electrically Erasable and Programmable Read Only Memory.) Typically, the problem tied to the necessity of biasing the floating gate (through its capacitive coupling with a control gate) and the semiconducting substrate in order to charge the floating gate and eventually discharge the electrical charge stored therein, has been satisfied by realizing a capacitive coupling zone between the floating gate and a drain region of the semiconducting substrate through a thin tunnelling oxide. Through such a tunnelling window, the flow of electrons from the isolated gate and the drain region of the substrate and vice-versa, during an erasing phase and during a programming phase, is obtained through a Fowler-Nordheim tunnelling mechanism by applying a sufficiently high voltage of one sign or of the opposite sign.
Bytewise erasability of EEPROM memories is achieved with a penalty in terms of compactness of the matrix of memory cells. Overall the cells are from three to four times larger than an EPROM cell, for the same fabrication technology, because they require a select transistor associated with each cell. The fabrication process of an EEPROM memory is notably much more complex of an EPROM process, and the EEPROM memory requires a relatively more complex overhead circuitry as well as the integration of voltage multipliers.
A schematic cross section of an EEPROM cell is shown in FIG. 1, while an electrical scheme of an EEPROM memory array is shown in FIG. 2, which contains also a table showing the typical operation voltages.
FLASH Memories
On the other hand, the improvement of fabrication technologies has allowed a further reduction of the thickness of the isolation dielectric between a floating gate and the monocrystalline silicon substrate while reliably ensuring a substantial absence of defects with an average growth thickness of the oxide of e.g. about 12 nm (120 .ANG.). This has permitted the development of the so-called FLASH memories.
The FLASH memory cell is programmable through a mechanism of injecting hot channel electrons into the floating gate, by biasing the control gate with a sufficiently high positive voltage (for example on the order of 12 V) and the drain with a voltage of about 6 V, in order to produce in the channel zone of the monocrystalline silicon substrate of the cell a strong electric field suitable to generate a current of highly energetic (hot) electrons within the silicon, capable of overcoming the potential barrier at the interface with dielectric and of being thereafter attracted toward the floating gate by the electric field.
Due to the extreme thinness of the normal gate dielectric, erasure can also be accomplished by applying a relatively high voltage (12 V) to the source region and maintaining the other electrodes to ground potential. Under these conditions the electrons that have been injected in the floating gate are able to cross the dielectric according to a Fowler-Nordheim tunnelling mechanism and "discharge" in the source region, during an erasing phase.
The possibility of electrically erasing the memory device without removing it from the printed circuit card for exposing it to UV light, has solved a most severe problem of traditional EPROM memories. With the overcoming of this limitation, all the intrinsic advantages and potentialities of EPROM memories, such as their extreme compactness, speed and above all their relatively low cost, have opened a vast field of application. On the other hand, since the FLASH memory cells have no select transistor, during an erasing phase, some cells rather than others, may reach a depletion state, assuming in practice a negative threshold. If this occurs, during a reading phase of the memory (i.e. with all wordlines grounded with the exception of the wordline to be read), not all the other cells of the addressed bitline would be non-conducting if any of these happened to have been depleted during a preceding erasing (a logic "zero" being the information stored in such cells) and this would cause reading errors.
For this reason, the erasing process of FLASH memories is intrinsically a critical process and is commonly carried out through a succession of pulses of an erasing bias voltage followed by a check until completing the erasing of all the cells of the memory while avoiding to inadvertently bring some of the cells to a depletion state. This erasing process engages in a non-negligible manner the microprocessor that is called to supervise the erasing process of the FLASH memory.
Thus the erasure of FLASH cells is quite different from that of EEPROM cells: because EEPROM cells which are provided with a select transistor, they can be erased to a uniform threshold, identical to the threshold of a virgin cell, under any condition.
Upon completing the erasing of the memory, individual FLASH cells assume a threshold of a value that is not uniform and constant but is normally contained within a certain range of variation. In other words there is a "dispersion" or spread of the threshold values of erased cells, the breath of which is tied also to parameters of the fabrication process. Such a spread of the threshold values of the cells must be taken into account by the circuitry that manages the memory.
For obviating this drawback of FLASH memories, a particular cell structure has been proposed, wherein each control gate line (wordline) of the memory array overlies (is capacitively coupled) only for a portion of its width, the relative floating gates of the cells of the row, while with a portion of its width the wordline constitutes the gate of as many select transistors, each associated to a respective memory cell of the row. In this way, though with a penalty in terms of compactness, a select transistor is associated to each cell, thus making uniform the threshold voltage of all the cells once the erasing of the memory array is performed. This technique is described in the paper entitled "A 128K FLASH-EEPROM using Double Polysilicon Technology" by George Samachisa, Chien-Sheng Su, Yu-Sheng Kao, George Smarandoiu, Ting Wong, Chenming Hu, presented at the IEEE International Solid-State Circuits Conference of Feb. 25, 1987, which is hereby incorporated by reference.
Use of Both FLASH and EEPROM
Notwithstanding the relatively good cost, speed and compactness of FLASH memories, there are some applications which also need, in addition to the FLASH, an EEPROM memory block (typically of much lower capacity) in which to store data that need to be frequently altered (updated).
These requirements generally occur in systems wherein:
Block-erasable FLASH memories have been proposed to meet these market demands. According to one of these techniques, the possibility of erasing the memory array by blocks is obtained by segmenting the source lines (source diffusions), the use of a further level of metal to define a further order of metal lines to which the portions or segments of source lines are connected through interconnection vias, and the realization of an additional decoder for selecting the blocks of the memory array to be erased. A system of this type is disclosed in U.S. Pat. No. 5,289,423, which is hereby incorporated by reference.
These techniques are intrinsically too inflexible to meet the requirements of different users in an optimum way, and imply a remarkable complication of the layout of the memory array because of the increased number of metal levels and of the need to form a large number of "by-passes" at cross points between orthogonal lines of the same level.
In the majority of cases, the requirements of the users could be satisfied in an optimum way by realizing an EEPROM memory block of sufficient size, in the same chip containing the FLASH memory, typically of much larger capacity, thus avoiding the need of employing two distinct memory devices.
On the other hand, there are obvious difficulties in compatibly integrating in the same device a FLASH memory and an EEPROM memory because of their structural diversity and of the different requisites in terms of voltage levels and current handling capacity of the ancillary circuitry. Problems of compatibility are even more marked in case of "single supply processes," in which different integrated charge pumps and voltage multipliers would be required in order to generate the relatively high voltages that are respectively needed during programming and erasing phases.
Even assuming that the compatibility problems can be overcome by adding steps to the fabrication process (e.g. by recourse to numerous additional masking steps), and by duplicating or multiplying the circuitry needed for generating the different voltages that are necessary during write, read and erase phases of the two different memory arrays, the yield of such a complicated process, and therefore the cost of the devices, would be discouraging with the present technology.
Alternative solutions that offer a pseudo EEPROM performance, though substantially realizing a FLASH memory, by exploiting software methods based on momentarily shifting the data on a different support, their correction and rewriting in the previously erased FLASH memory array, are also burdensome in terms of the time that is required to the system's microprocessor.
Therefore there is a clear need and/or utility of being able to realize on a same chip an EEPROM type memory block in a totally compatible manner with a FLASH memory, through a standard single-supply FLASH fabrication process, without any modification thereof.
Even in the case of stand alone EEPROM type (i.e. erasable by bytes) memory devices, i.e. devices which are not necessarily integrated on the same chip together with a FLASH memory, the possibility of realizing them by a standard FLASH fabrication process, may in many cases represent a great advantage in terms of standardization of fabrication processes and production economy for families of devices or for complementary devices.
This important objective is fully met by the present invention, which offers also other important advantages.
Innovative EEPROM Compatible with FLASH Process and Voltages
The disclosed inventions provide a way to combine FLASH and EEPROM arrays on a single chip, using a normal single-supply FLASH process. The byte erasable (EEPROM) memory array employs an array of FLASH cells organized in rows and columns and individually addressable (during a programming and a reading phase) through a plurality of wordlines and bitlines, according to a normal architecture of nonvolatile memories.
Therefore the mechanism of programming (writing) the cells remains that of a normal FLASH cell, that is injection of hot electrons from the channel region into the floating gate of the cell that takes place in a zone close to the drain diffusion, while in an erasing phase the mechanism used is the Fowler-Nordheim tunnelling mechanism, that takes place in an overlap zone of the floating gate on the source region of the cell.
Byte erasability of the EEPROM memory array is provided by realizing an auxiliary byte selection structure that comprises a byte selection transistor, to a first current terminal of which are connected in common the sources of the cells of a row of the matrix that compose a certain byte, and which has its other current terminal connected to a respective line of a plurality of source biasing lines that are individually selectable by the control circuitry of the memory array. The select transistors of the bytes arranged along the same row of the array have their gate driven in common through a respective line of a number of select lines identical to the number of wordlines of the memory array.
Erasing of a certain byte takes place by biasing, through the byte select transistor connected in series with the sources of the memory cells of the selected byte to be erased, the sources of the cells and the relative wordline (control gate of all the cells of the row containing the byte selected for erasing) with a voltage sufficient to generate a Fowler-Nordheim (FN) tunnelling current of electrons from the floating gate of the cells to their respective source region, while dividing the applied voltage. In practice, to the particular wordline is applied a negative voltage having a value insufficient to cause soft-erasing disturbances on the other unselected memory cells of the same wordline, while a positive, "complementary", voltage is applied to the sources, through the byte select transistor, that is a positive voltage whose value if related to the tunnelling voltage, is reduced by the absolute value of the negative voltage that is applied to the control gate (multiplied by the capacitive ratio of the floating gate cell structure). During an erasing phase, the drains of the cells may be kept at ground potential or be left floating.
According to the parameters of a typical fabrication process of a FLASH memory device, the voltage applied to a wordline during an erasing phase may be of about -5 V while the voltage applied to the sources of the cells of the byte to be erased may be comprised between about 8 V and 9 V. In this way, a voltage difference of about 12 V-13 V is realized while reducing the electrical stress on the other cells of the wordline down to a level that has been found tolerable for the entire period necessary to sequentially erase-all the bytes of a wordline. A voltage of about 3 V may concurrently by applied to all the other (unselected) wordlines.
Conversely, programming of the cells may take place by applying the same voltages as in a normal FLASH memory. Normally, a positive voltage of about 12 V is applied to the wordline (control gate) while to the drain of the cells to be programmed a positive voltage comprised between 5 V and 6 V may be applied through the relative bitlines of the memory matrix. The common source of the cells of the byte selected for programming is grounded through the byte select transistor, while the sources of all the other cells of the same wordline may advantageously be biased, through their respective byte select transistors, at a positive voltage of an intermediate value, for example of about 3 V, to help inhibit soft programming disturbances on unselected cells of the same wordline.
Advantageously the same charge pump or voltage multiplier circuits are used for the FLASH and EEPROM arrays. The only additional requirement is the integration of a charge pump for generating a negative voltage comprised between about -5 V and -8 V, in order to "split" the voltage difference that must be imposed between the control gate and the source of the cells selected for erasing, according to the above described manner. However, this additional negative voltage pump has substantially negligible power requisites, since it is used merely to bias a control gate (wordline).
Of course, the charge pump used for generating the positive voltage for biasing the control gates (wordlines) during programming, which may be of about 12 V, is also an essentially low absorption charge pump, while the charge pump for generating the positive voltage of about 5 V-6 V to be applied to the bitlines of the selected cells for programming, in case of a single supply device designed for operation with relatively low supply voltage (for example about 3 V in the case of battery operable systems) must be designed so as to satisfy the required power requirements. In fact, in this case, the biasing of the drain of a selected cell for programming to a level sufficient to accelerate the channel charge carriers up to sufficiently high kinetic levels (i.e. production of channel hot electrons), produces a non-negligible current through the cell's channel. In case of single supply (for example a 5.+-.10% V or a 3.3.+-.10% V device), such a power requisite may be satisfied directly from the supply.
During a programming phase of the cells, considerations tied to the voltage drops along the current path may limit the programming to few bits at the time, for example to only two bits at the time. In fact, the resistance of the programming current path, for example to the "farthest" cell of an octet of cells constituting a selected byte for programming, may have reached one to several hundreds ohms and the voltage drop, in consideration of the relatively high current (in the vicinity of about 100-500 .mu.A per cell), could become excessive if all the cells of the byte are written in parallel.
Nevertheless the EEPROM memory block may offer an "ERASE-ALL" function, in a completely compatible way.
The increased power needed for implementing an erase-all function of the EEPROM memory block may be provided by exploiting either the supply or the high power charge pump circuit destined to generate the voltage of about 5 V-6 V necessary for biasing the drain during the writing of the cells for biasing through the respective byte select transistors the sources and incrementing the absolute value of the negative voltage for biasing the wordlines from the value of about -5 V used for byte erasing to a value of about -8 V, thus ensuring also during an ERASE-ALL phase a voltage difference of about 12 V between the source and the control gate of the memory cells.
The use of a byte select transistor functionally connected in series with the source of the memory cells (instead of being connected in series with their drain) produces also the important result of ensuring a perfect uniformity of the threshold of the erased cells by preventing them from assuming a negative threshold because of the reaching by any of them of a depleted state during an erasing phase.
This greatly simplifies the erasing process by reducing the burden of supervision of the microprocessor and makes the management of the memory block substantially similar to that of a matrix of EEPROM cells.
Another important aspect of the architecture of the EEPROM block of the invention resides on the fact that each select line to which the gates of all the byte select transistors of the bytes arranged along the same row of FLASH memory cells are connected, is always selected together with the respective wordline of the row of memory cells, during any phase of operation of the memory block. This eliminates the need of implementing an additional logic decoder for selecting the select lines (i.e. the byte select transistors) by being able to employ for this purpose the same logic decoder of the wordlines. Of course, to the wordline and to the respective select line that may be logically selected by a single decoder, different voltages will be applied during the various phases of operation of the memory.
Thus the disclosed inventions permit combination of a byte erasable memory block, with the same functionality of a conventional EEPROM memory, in a fully compatible manner with a normal fabrication process of a FLASH memory device with single supply, without requiring any additional process steps.